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MP4651 off line led driver MP4651 rev.1.0 www.monolithicpower.com 1 1/13/2011 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. the future of analog ic technology description the MP4651 is a high performance off-line led driver designed for powering the leds especially for high power isolated application. the MP4651 utilizes fixed operating frequency pwm control. it outputs two 180 degree phase shifted driving signals for various external power stages. its enhanced 9v gate driver provides adequate driving capability for the external mosfets and directly drives the external gate driving transformer. the MP4651 implements fast and high contrast ratio pwm dimming to the leds. pwm dimming is controlled with either an external dc voltage or pwm signal. the burst dimming frequency can be synchronized to an external synchronizing signal. the built-in fault management features include open led protection, short led protection, over voltage protection, and over temperature protection. the protection interface is flexible for various setups and is easy to use. MP4651 integrates a delay timer to recover the system. the MP4651 is available in a 16-pin soic package. features ? 9v enhanced gate driver ? programmable fixed operating frequency ? input voltage range from 9v to 30v ? dc or pwm input dimming control ? burst dimming frequency synchronization ? smart fault protection interface ? built-in fault management ? built-in delay timer for system recovery ? available in a soic16 package applications ? lcd tv and lcd monitor ? flat panel video displays ? led lighting applications for mps green status, please visit mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks o f monolithic power systems, inc. the MP4651 is covered by us patents 6,683,422, 6,316,881, and 6,114,814. other patents pending.
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 2 1/13/2011 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. simplified typical application circuit vin en dim 400v gnd 400v ref ref fb ovp 10 11 12 . . . fb ovp ocp pwmout pwmout sync en fb vcc bfs fset ft gnd gl pwmout vin gr ovp pwmin comp 1 2 3 4 5 6 7 8 9 MP4651 13 14 15 16 ssd sync sync sync ocp 400v gnd
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 3 1/13/2011 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. ordering information part number* package top marking free air temperature (t a ) MP4651es soic16 MP4651es -20 c to +85 c * for tape & reel, add suffix ?z (e.g. MP4651es?z) for rohs compliant packaging, add suffix ?lf (e.g. MP4651es?lf?z) package reference ovp sync ssd fb gr gnd gl vcc 1 2 3 4 16 15 14 13 vin en pwmin bfs 12 11 10 9 comp ft pwmout fset 5 6 7 8 top view pin 1 id absolute maxi mum ratings (1) input voltage v in .......................................... 35v gl, gr ......................................... -0.3v to 10.7v fb, ssd ....................................... - 5.8v to +5.8v other pins .................................... - 0.3v to +6.5v continuous power dissipation (t a = +25c) (2) ??????????????????.2.5w junction temperature ............................... 150 c lead temperature (solder)....................... 260 c operating frequency .............. 20khz to 150khz storage temperature ............... - 55 c to +150 c recommended operating conditions (3) input voltage v in ................................. 9v to 30v operating frequency (typical) ................ 50khz maximum junction temp. (t j ) .............. +125 c thermal resistance (4) ja jc soic16 ................................... 80 ...... 30 ... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max)=(t j (max)- t a )/ ja . exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 4 1/13/2011 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. electrical characteristics v in = 12v, t a = +25 c, unless otherwise noted. parameter symbol condition min typ max units gate driver gl, gr gate pull-down r gd 2 ? gate pull-up r gu 4 ? output source current i source 1 a output sink current i sink 2 a maximum duty cycle d max 46% en en turn on threshold v en-on 2 v en turn off threshold v en-off 1 v internal pull-down resistor r en-in 60 k ? brightness dimming control range pwm full scale v pwm dc input burst dimming 1.1 1.2 1.3 v pwm logic input threshold v th-pwm pwm dimming 1.6 1.9 2.2 v pwm logic input hysteresis v th-pwm-h y st pwm dimming 0.1 v burst frequency set (bfs) source current i src ( bfs ) v bfs = 2v 120 140 170 a lower threshold v v ( bfs ) 2.2 2.4 2.6 v upper threshold v p ( bfs ) 3.3 3.55 3.8 v supply current supply current (enabled) i in-en no driver output 1.5 2.5 ma supply current (disabled) i in-off v in =30v 1 a operating frequency f o 25k ? fset to gnd 46.5 50 53.5 khz frequency set voltage v fset 1.14 1.2 1.25 v output pwm dimming signal for led (pwmout) logic high voltage v h-pwmout normal operation 5v 6 6.5v v logic low voltage v l-pwmout at fault condition, 25k ? fset to gnd 0.1 0.6v v output pwm source current i source pwmout 100pf on pwmout pin 3 ma output pwm sink current i sink pwmout 100pf on pwmout pin 20 ma led current feedback (fb) magnitude |v fb | 0.57 0.6 0.63 v input resistance r fb in 30 k ? over voltage protection (ovp) over voltage protection threshold v th(ovp) 2.22 2.38 2.55 v
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 5 1/13/2011 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. electrical characteristics (continued) v in = 12v, t a = +25 c, unless otherwise noted. parameter symbol condition min typ max units fault timer (ft) threshold v th ( ft ) 2.2 2.4 2.6 v source current i source ( ft ) 8 a comp clamp voltage v comp 0.60 v reference current i comp+ 20 a pull down current at fault condition i comp-fault fault mode is triggered 30 a burst frequency synchronization (sync) high logic level v sync-h 1.4 v low logic level v sync-l 0.7 v pulse width t s y nc 6 10 20 s synchronizing frequency f sync dc input burst dimming, compared to the frequency f bfs set by bfs pin r and c 110% 120% fault detection threshold (ssd, fb) ssd threshold v ssd 2.22 2.36 2.55 v ssd detection delay time t d ssd 7 s fb threshold v fb th 1.1 1.2 1.3 v fb detection delay time t dfb 7 s output gate driver (vcc) voltage v vcc no load 8.7 9.7 10.5 v current i vcc 20 ma
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 6 1/13/2011 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. pin functions pin # name description 1 ovp over voltage protection. the output voltage is sensed by this pin through a voltage divider from the anode of the led to ground. if the voltage at ovp exceeds 2.38v for 7us, the fault mode is triggered. 2 sync synchronization for the burst dimming frequency . applying a synchronizing signal with a narrow pulse on this pin will synchronize the burst frequency on bfs pin. the frequency of the synchronizing signal should be highe r than the frequency set by bfs pin. 3 ssd short string detection. a comparator is integrated in this pin for short string protection. if the voltage on this pin gets lower than 2.36v for 7us, the fault mode is triggered. 4 fb led current feedback input. connect this pin to the cathode of the led and shunt a sense resistor to ground. the internal error amplifier sinks a current from the comp pin proportional to the absolute value of the voltage at this pin. the average voltage at this pin is regulated to 0.6v reference voltage. the voltage on this pin is also used for shor t string detection. when the voltage on this pin gets higher than 1.2v for 7us, the ic recognizes th is as short string condition and triggers the fault mode. 5 comp feedback compensation node. connect a compensation capacitor or a r-c network from this pin to gnd. 6 ft fault timer. connect a timing capacitor from this pin to gnd to set the fault timer to recover the system. when the voltage on this pin gets higher than the 2.38v threshold, the ic recovers. 7 pwmout this pin outputs the pwm dimming signal to le d for fast dimming. at fault mode, the pwmout is pulled down. 8 fset frequency set. connect a resistor from this pi n to gnd. this resistor sets the operating frequency of the MP4651. a 25kohm resistor se ts the operating frequency at typical 50khz. 9 bfs burst frequency set. connect a resistor in parallel with a capacitor from bfs to gnd. the resistor and capacitor programs the burst dimmi ng frequency. if the burst dimming is to be controlled by an external pwm signal, pull up bfs to vcc through a 20k ? resistor and apply the pwm signal to the pwmin pin. 10 pwmin burst-mode (digital) brightness control input. for dc input burst dimming, the voltage range from 0 v to 1.2v at pwmin linearly sets the burst-mode duty cycle from 0 to 100%. for external pwm input dimming, directly apply t he logic signal on this pin. the MP4651 has positive dimming polarity. 11 en enable input. pull en high to turn on th e chip, and pull en low to turn it off. 12 vin supply voltage input. 13 vcc linear regulator output and bias supply of the gate driver. it provides the supply for the gate driver and also the external control circui t, the typical value is 9.7v. bypass vcc with a 1 f or larger ceramic capacitor. 14 gl driving signal output, 180 degree phase shifted of gr 15 gnd ground. 16 gr driving signal output, 180 degree phase shifted of gl
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 7 1/13/2011 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. block diagram ovp fb fset comp 1 4 5 8 0.6v 2.38v ssd 3 2.36v pulse width modulation pwmin 10 pwmout 7 driver en 11 ft 6 2.38v gr 16 gate driver gl 14 vin 12 regulator vcc 13 gm 1.2v dc l/r bfs 9 sync 2 burst dimming signal generator fault management figure 1?MP4651 block diagram
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 8 1/13/2011 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. design information steady state and enable control the MP4651 is a fixed operating frequency off- line led driver, specifically designed for the high power isolated applications. powered by 9v to 30v input supplies, the MP4651 outputs two 180 degree phase shifted driving signals for the external power stages. its enhanced 9v gate driver provides adequate driving capability to the external mosfets and directly drives the external gate driving transformer. the MP4651 utilizes pulse width modulation control to the system. the operating frequency is set by an external resistor connected from fset pin to gnd. the led current is fed back to fb pin and compared with internal 0.6v reference voltage. together with the integrator compensation network on comp pin, which is connected to the output of the error amplifier, the output led current is accurately regulated. the voltage on comp pin is compared with the internal oscillator and generates duty cycle modulated signals to control the external power switches. the system power is controlled by en pin. when the chip is enabled, the built-in regulator for vcc is powered up and the internal circuit starts. brightness control MP4651 implements burst dimming (digital brightness) of the led. the MP4651 has a built- in burst oscillator which can generate a triangle waveform on the bfs pin. burst dimming can be achieved by either a dc voltage input or external pwm signal. when burst dimming with a dc input voltage, add a capacitor in parallel with a resistor on bfs pin to set the burst frequency and apply the dc voltage on the pwmin pin to program the burst duty cycle. the burst frequency can be synchronized to an external frequency. applying a synchronizing frequency signal with narrow pulse on sync pin can synchronize the burst frequency. the synchronizing frequency should be higher than the burst frequency set by the bfs pin. please refer to sync pin description for details. when burst dimming with external pwm signal, pull up bfs pin to vcc through a 20k ? resistor and apply the pwm signal on pwmin pin. fast and high contrast ratio pwm dimming the MP4651 implements fast and high contrast ratio pwm dimming to the wled. the pwm dimming signal (controlled by a dc input voltage or direct pwm signal) is outputted on pwmout pin to drive the external mosfet in series with the leds, therefore the led current rises up immediately when pwm dimming signal is effective. the pwm dimming signal is also used to disconnect the compensation network (on comp pin, a capacitor or a r-c network) from the error amplifier at pwm off interval, and so that the compensation network voltage is hold at this interval and gets nearly immediately to the steady state value when pwm signal is effective. it eliminates the control loop response time and realizes fast dimming. the MP4651 strictly controls the sequence of the driving signals. both the sequence of gl and gr signals and the delay time between pwm dimming signal and driving signals are accurately fixed. therefore, for each time of pwm dimming, the driving signals are exactly the same and so does the output power delivered to the load. it eliminates the possibility of flicker at small pwm dimming pulse and thus realizes the high contrast ratio pwm dimming. pwmout i led pwmin comp figure 2?fast and high contrast ratio pwm dimming
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 9 1/13/2011 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. fault protection system fault management facilities include the over voltage protection, short string protection and a delay timer for system recovery. the output voltage is monitored by the ovp pin through a voltage divider. once the voltage on ovp pin exceeds 2.38v for 7us, the MP4651 recognizes this as open condition and triggers fault mode. the ssd pin is used for short string detection. when the voltage on ssd pin gets lower than 2.36v for 7us, the MP4651 recognizes this as short string condition and triggers the fault mode. fb pin also functions as short string protection. when the voltage on fb pin is higher than 1.2v for 7us, the ic triggers the fault mode. at fault mode, the outputs of the gate drivers gl and gr are disabled, the pwmout signal is pulled down and the comp capacitor is discharged by a 30ua sourcing current. the fault timer is started. an 8ua current source charges the ft capacitor, and when ft voltage hits 2.38v, system recovers. it enables the output driving signals, releases the comp, resets the fault flag and pulls down the ft pin.
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 10 1/13/2011 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. application information pin 1 (ovp): over voltage protection: this pin is used for over voltage protection. the output voltage is monitored by this pin and when the voltage on this pin exceeds 2.38v for 7us, the fault mode is triggered. pin 3 (ssd): short string detection: this pin is used for short string protection, when the voltage on this pin gets lower than 2.36v for 7us, the ic treats it as short string condition and triggers the fault mode. pin 4 (fb): led current feedback. this pin is used for led current regulation. the voltage on this pin is regulated with 0.6v average value. fb pin also functions as short sting protection. when the voltage on fb gets higher than 1.2v for 7us, the ic triggers the fault mode. pin 5 (comp): this pin is used for compensation. connect a 1~47nf capacitor from comp to gnd. this cap should be x7r ceramic. the value of this cap determines the stability of the led current regulation. pin 6 (ft): connect a capacitor from this pin to gnd to set the fault timer. it sets the time to recover the system when a fault condition is detected. ft ft 2.38v c t 8ua = a 10nf capacitor on ft sets the delay time around 3ms pin 8 (fset): connect a resistor from this pin to gnd to set the operating frequency (f o ). the value for this resistor r1 is calculated by 9 o 1.25 10 r1 f = for r1 = 25k ? , operating frequency will be 50khz. pin 7 (pwmout): this pin outputs the burst dimming signal to the led for fast pwm dimming. connect this pin directly to the gate of the dimming mosfet in series of the led. pin 10 (pwmin): this pin is used for burst brightness control. for dc input burst dimming, the dc voltage on this pin controls the burst percentage on the output. the signal is filtered for optimal operation. a voltage ranging from 0 to 1.2v on pwmin programs the burst dimming duty cycle from 0 to 100%. for direct pwm burst dimming, pull bfs high to vcc through a 20k ? resistor and connect pwmin pin to a logic level pwm signal. logic high is burst on and a logic low is burst off. pin 9 (bfs): bfs pin is used to set the burst dimming frequency. connect a resistor (r bfs ) in parallel with a capacitor (c bfs ) on this pin to set the burst dimming frequency, as shown in figure 3. bfs 2.4v 3. 55v burst dimming signal i le d burst dimming frequency rising time figure 3?burst mode with dc input voltage at pwmin pin these values are determined as follows: set a percentage of the rising time, where: rise rise burst dtf = r bfs and c bfs are determined by: bfs rise 1 r 21.16k 1 21.43k d ?? ?+ ?? ??
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 11 1/13/2011 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. rise bfs burst bfs 1d c f r 0.405 ? = for d rise = 0.1, f burst = 200hz, then r bfs = 212k, c bfs = 52nf for direct pwm burst dimming, pull bfs high to vcc through a 20k ? resistor and apply the pwm signal to pwmin pin. pin 2 (sync): burst frequency synchronization. this pin is used to synchronize the burst dimming frequency. applying a synchronizing frequency signal with small pulse will synchronize the burst frequency. sync en fb vcc bfs fset ft gnd gl pwmout vin gr ovp pwmin comp 1 2 3 4 5 6 7 8 MP4651 14 15 16 ssd 10 11 12 sync signal 9 ref 13 a bfs i led burst dimming signal 1.2v 3.55v 2.4v sync signal a figure 4?synchronized dc input burst dimming figure 4 shows the synchronized dc input burst dimming. the synchronizing signal is filtered by a high pass filter. its rising edge is caught and used for synchronizing the triangle waveform on bfs pin. the synchronizing frequency should be higher than that set by bfs pin and the amplitude of the synchronizing signal should be higher than 1.4v. table 1?function mode function pin connection pwm bfs sync burst mode with dc input voltage 0v to 1.2v c bfs , r bfs gnd burst mode with dc input voltage and synchronizing frequency 0v to 1.2v c bfs , r bfs r,c,d network burst mode with external pwm source pwm to vcc through 20k ? resistor gnd burst brightness polarity: 100% duty cycle at pwm voltage 1.2v. pin 11 (en): pull this pin high to enable the chip, and pull it low to disable the chip. pin 12 (vin): supply voltage input. bypass the supply voltage with a 0.1uf or greater ceramic cap. this cap should be placed close to the ic. pin 13 (vcc): this pin provides the gate driver supply voltage, its typical value is 9.7v. connect a 1uf or greater ceramic capacitor on this pin to bypass the supply voltage. this voltage is also used to supply the external control circuit. pin 14(gl), pin 16 (gr): gate driving signals output. gl and gr are 180 degree phase shifted driving signals. with its enhanced driving capability, gl and gr are able to directly drive the externally mosfet in the off- line system through a gate driving transformer. connect two 5 ? resistors in series with gl and gr to reduce the emi noise. a 2.2nf y capacitor is recommended to be placed between the primary reference ground and secondary reference ground.
MP4651?off line led driver notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP4651 rev. 1.0 www.monofbthicpower.com 12 1/13/2011 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. package information soic16 0.016(0.41) 0.050(1.27) 0 o -8 o detail "a" 0.010(0.25) 0.020(0.50) x 45 o see detail "a" 0.0075(0.19) 0.0098(0.25) 0.150 (3.80) 0.157 (4.00) pin 1 id 0.050(1.27) bsc 0.013(0.33) 0.020(0.51) seating plane 0.004(0.10) 0.010(0.25) 0.386( 9.80) 0.394(10.00) 0.053(1.35) 0.069(1.75) top view front view 0.228 (5.80) 0.244 (6.20) side view 1 8 16 9 recommended land pattern 0.213 (5.40) 0.063 (1.60) 0.050(1.27) 0.024(0.61) note: 1) control dimension is in inches. dimension in bracket is in millimeters. 2) package length does not include mold flash, protrusions or gate burrs. 3) package width does not include interlead flash or protrusions. 4) lead coplanarity (bottom of leads after forming) shall be 0.004" inches max. 5) drawing conforms to jedec ms-012, variation ac. 6) drawing is not to scale. 0.010(0.25) bsc gauge plane

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